Array substrate of liquid crystal display and fabrication method thereof

ABSTRACT

Provided is an array substrate of an LCD that includes a substrate, an active layer, a first insulating layer, and a gate electrode sequentially formed on the substrate. A source region and a drain region reside in predetermined regions of the active layer and each is doped with impurity ions. A second insulating layer overlies an entire surface of the substrate including the gate electrode. A pixel electrode resides on the second insulating layer. First and second contact holes reside in the first and second insulating layer and expose portions of the source region and the drain region, respectively. A portion of a source electrode contacts the source region through the first contact hole and a first portion of a drain electrode contacts the drain region and a second portion contacts the pixel electrode.

PRIORITY CLAIM

This application claims benefit of priority to Korean Application No.24856/2004, filed in Korea on Apr. 12, 2004, the disclosure of which isincorporated by reference herein.

BACKGROUND

1. Technical Field

The present invention relates to an array substrate of a liquid crystaldisplay device (LCD), and more particularly, to an array substratehaving a polysilicon thin film transistor (TFT)-LCD which is fabricatedusing a diffraction exposure process, and a fabrication method thereof.

2. Description of the Related Art

Until recently, a cathode ray tube (CRT) has been most widely used amongdisplay devices for displaying image information on a screen. The CRT,however, has may inconveniences owing to a large volume and weightcompared with the display area. To this end, a thin flat panel displayhas been developed that can be used anywhere, because it has a largedisplay area and has a very thin profile. The flat panel display is nowreplacing the CRT. In particular, a liquid crystal display (LCD)exhibits higher resolution than other flat panel displays, and has arapid response speed that is comparable to the display quality of theCRT when displaying moving images.

In operation, the LCD utilizes optical anisotropy and polarization. Inother words, an alignment direction of the liquid crystal molecules iscontrollable by artificially applying an electromagnetic field to theliquid crystal molecules, which are thin and long in their structure andare directionally aligned.

The ability to artificially control their alignment direction allows thealignment direction of the liquid crystal molecules to be changed andthe light that is polarized due to the optical anisotropy to can bemodulated. Accordingly, the LCD is capable of displaying imageinformation through the application of an electromagnetic field.

An active matrix liquid crystal display includes thin film transistors(TFTs) and pixel electrodes connected with the TFTs that are arranged ina matrix configuration. The active matrix LCD is being widely used dueto its high resolution and superior moving picture reproductioncapability.

A base element of the LCD is the liquid crystal panel, which will now bedescribed with reference to the accompanying drawing.

FIG. 1 is a partial exploded perspective view of a typical LCD. Ingeneral, an LCD 11 includes an upper substrate 5 and a lower substrate22. The upper substrate 5 includes a black matrix layer 6, a colorfilter layer 7, including sub-color filters of red (R), green (G) andblue (B), and a transparent common electrode 18 formed on the colorfilter layer 7. The lower substrate 22 includes pixel regions (P), pixelelectrodes 17 formed on the pixel regions (P) and an arrayinterconnection line including switching elements (T). Between the uppersubstrate 5 and the lower substrate 22, there is interposed a liquidcrystal layer 15, described above.

The lower substrate 22 is known in the art as an “array substrate.” Onthe lower substrate 22, a plurality of thin film transistors thatfunction as switching elements are arranged in a matrix configuration,and gate lines 13 and data lines 15 are formed to cross the plurality ofthin film transistors. Also, the pixel regions (P) are defined by thecrossing pattern of the gate lines 13 and the data lines 15.

The pixel electrode 17 formed on the pixel region (P) is made of atransparent conductive material having a superior light transmittancesuch as indium-tin-oxide. (ITO).

The LCD 11 configured as described above, displays images when theliquid crystal molecules of the liquid crystal layer 14 on the pixelelectrode 17 are aligned by a signal applied via the thin filmtransistors. The liquid crystal molecules are aligned in such a way asto control the amount of light passing through the liquid crystal layer14.

FIG. 2 is a partially magnified plan view of some pixels of a relatedart LCD array substrate. The array substrate employs a p-Si TFT. Inother words, TFTs employed in LCDs are classified into amorphous silicon(a-Si) TFTs and polycrystalline silicon (p-Si) TFTs depending oncrystalline state of the semiconductor layer serving as an activechannel.

In a p-Si TFT, the driving frequency of a driving circuit thatdetermines the number of the driving pixels can be advantageouslyenhanced and thus high definition capability is possible because the TFThas high field effect mobility. Also, in the p-Si TFT, enhanced picturequality can be expected because the charge time of a signal voltage tothe pixel regions is reduced and thus distortion of transfer signals isreduced. Further, the p-Si TFT has an advantage of low power consumptionbecause it can be driven at a voltage less than 10 V, compared with thea-Si TFT, which has a relatively higher driving voltage (about 25V).

Referring to FIG. 2, a plurality of gate lines 111 and a plurality oforthogonal data lines 112 are arranged in a matrix configuration,thereby defining pixel regions (P).

At cross points of the data lines 112 and the gate line 111, the TFTs(T) each include a semiconductor layer 116, a gate electrode 120, asource electrode 126 and a drain electrode 128, and pixel electrodes 134electrically connected with the TFTs.

The semiconductor layer 116 is electrically connected with the sourceelectrode 126 and the drain electrode 128 through first and secondsemiconductor layer contact holes 122 a and 122 b, and the drainelectrode 128 is electrically connected with the pixel electrode 134through a drain contact hole 130.

The semiconductor layer 116 is formed by depositing an amorphous (a-Si)film on the substrate and crystallizing the deposited a-Si film usinglaser annealing to form polycrystalline silicon.

FIGS. 3A through 3G are sectional views schematically illustrating aprocess flow to obtain the LCD array substrate of FIG. 2, in which thesectional views are taken along the line A I-I′ of FIG. 2. In theprocess shown in FIGS. 3A through 3G, an array substrate employing ap-Si TFT is used, and respective patterns are formed by transferringpatterns of a mask onto a substrate having a thin film formed thereon.For example, a photolithography process is used that includesphotoresist coating, mask alignment, exposure of the photoresist throughthe mask, and development of the photoresist.

Referring to FIG. 3A, a buffer layer 30 is formed on the entire surfaceof an insulating substrate 1 using a first insulating material, and apolysilicon active layer 32 a is then formed on the buffer layer 30using a first mask process.

The active layer 32 a is formed by depositing an amorphous silicon layeron the buffer layer 30, performing dehydrogenation of the amorphoussilicon layer, and crystallizing the amorphous silicon layer intopolysilicon layer by a heat treatment.

Referring to FIG. 3B, after the process of FIG. 3A, a second insulatingmaterial and a first metal film are sequentially deposited and patternedby a second mask process to form a gate insulating layer 36 and a gateelectrode 38 at a middle portion of the active layer 32 a (shown inFIGS. 3D and 3E).

Also, to form a channel region and a heavily impurity-doped source anddrain regions in the active layer 32 a, both exposed edges of the activelayer 32 a are ion-doped using the gate electrode 38 as a mask.

Referring to FIG. 3C, after the process of FIG. 3B, a first insulatinglayer 40 is formed of a third insulating material on a resultantstructure of the substrate 1.

Referring to FIG. 3D, after the process of FIG. 3C, a third insulatingmaterial is deposited and then patterned by a third mask process to forma second insulating layer 44 having first and second ohmic contact holes46 a and 46 b that partially expose both edges of the active layer 32 a.Alternatively, the first and second insulating layers 40 and 44 may beformed as a single layer.

In both edges of the active layer 32 a, the left edge is a source region1 a connected with a source electrode to be formed by a subsequentprocess and the right edge is a drain region 1 b to be connected with adrain electrode. Next, both exposed edges of the active layer 32 a areheavily doped with impurity ions to form ohmic contact layers 32 b and32 c.

Next, referring to FIG. 3E, a third metal film is deposited and thenpatterned by a fourth mask process to form a drain electrode 50 and asource electrode 52. At this time, the drain electrode 50 is connectedwith the ohmic contact layer 32 c of the drain region Ib through thefirst ohmic contact hole (46 a of FIG. 3D), and the source electrode 52is connected with the ohmic contact layer 32 b of the source region Iathrough the second ohmic contact hole (46 b of FIG. 3D).

In this process, a TFT (T) is formed that includes the semiconductorlayer 32, the gate electrode 38, and the source and drain electrodes 52and 50. The gate electrode 38 is connected with the gate line (notshown), and the source electrode 52 is connected with the data line (notshown).

Next, referring to FIG. 3F, after the process of FIG. 3E, a fourthinsulating material is deposited on a resultant structure of thesubstrate 1 and then patterned by a fifth mask process to form a thirdinsulating layer 54 having a drain contact hole 56.

Next, referring to FIG. 3G, an indium tin oxide (ITO) transparentconductive layer is deposited on a resultant structure of the substrate1 including the drain contact hole 56 and then patterned by a sixth maskprocess to form a pixel electrode 62. The indium tin oxide forms a lowresistance contact with a metal when a TAB bonded.

As described above, the related art LCD array substrate is fabricated bysix masking steps.

The respective mask processes represent a series of processes forforming a desired pattern in a thin film formed on a substrate. Eachmasking process transfers a pattern of a mask onto the thin film andincludes the steps of photoresist coating, exposure, and developing, andthe like.

As the number of the mask processes increases, production yield islowered and the probability of incurring defects is increased. Also,since masks designed for forming patterns are very expensive, theincrease in the number of the masks used in the fabrication of the arraysubstrate increases the fabrication costs of the LCD.

SUMMARY OF THE INVENTION

Accordingly, the present invention is directed to an array substrate ofan LCD and fabrication method thereof that substantially obviates one ormore problems due to limitations and disadvantages of the related art.

In accordance with an embodiment of the invention, there is provided anarray substrate of an LCD including a substrate. An active layer, afirst insulating layer, and a gate electrode sequentially are formed onthe substrate. A source region and a drain region reside inpredetermined regions of the active layer and each is doped withimpurity ions. A second insulating layer overlies an entire surface ofthe substrate including the gate electrode. A pixel electrode resides onthe second insulating layer. First and second contact holes reside inthe first and second insulating layer and expose portions of the sourceregion and the drain region, respectively. A portion of a sourceelectrode contacts the source region through the first contact hole anda first portion of a drain electrode contacts the drain region and asecond portion of the pixel electrode.

According to another aspect of the present invention, there is provideda method of fabricating an array substrate of an LCD. The methodincludes sequentially forming an active layer, a first insulating layer,and a gate electrode on a substrate. A source region and a drain regionare formed on predetermined regions of the active layer by implantingimpurity ions into the predetermined regions of the active layer. Asecond insulating layer is formed on an entire surface of the substrateincluding the gate electrode. A pixel electrode is formed on the secondinsulating layer, and first and second contact holes are formed byremoving a portion of the first and second insulating layer overlyingthe source region and the drain region. A source electrode is formed inwhich a portion contacts the source region through the first contacthole, and a drain electrode is formed in which a first portion contactsthe drain region and a second portion contacts the pixel electrode.

According to a further aspect of the present invention, there isprovided a method of fabricating an array substrate of an LCD. Themethod includes forming an active layer on a substrate using a firstmask process and depositing a first insulating layer and a first metallayer on the substrate. The first metal layer is patterned using asecond mask process to form a gate electrode. A source region and adrain region are formed on predetermined regions of the active layer byimplanting impurity ions into the predetermined regions of the activelayer. A second insulating layer and a transparent conductive film aredeposited on an entire surface of a resultant substrate including thegate electrode. A portion of the first and second insulating layers andthe transparent conductive film are removed using a third mask processto form first and second contact holes partially exposing the source anddrain electrodes, and a pixel electrode. A second metal layer isdeposited on the substrate and patterned using a fourth mask process toform a source electrode and a drain electrode, such that the sourceelectrode is connected to the source region through the first contacthole and the drain electrode is connected to the drain electrode throughthe second contact hole.

It is to be understood that both the foregoing general description andthe following detailed description of the present invention areexemplary and explanatory and are intended to provide furtherexplanation of the invention as claimed.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which are included to provide a furtherunderstanding of the invention and are incorporated in and constitute apart of this application, illustrate embodiment(s) of the invention andtogether with the description serve to explain the principle of theinvention. In the drawings:

FIG. 1 is a partial exploded perspective view of a related art LCD;

FIG. 2 is a partially magnified plan view of some pixels of a relatedart LCD array substrate;

FIGS. 3A through 3G are sectional views schematically illustrating aprocess flow of a related art LCD array substrate;

FIGS. 4A through 4F are sectional views schematically illustrating aprocess flow of an LCD array substrate according to an embodiment of thepresent invention;

FIGS. 5A through 5E are sectional views exemplarily illustrating a thirdmask process described in FIG. 4C according to an embodiment of thepresent invention;

FIG. 6 is a partial plan view of a diffraction mask used in afabrication method of an LCD array substrate according to an embodimentof the present invention;

FIGS. 7A through 7C are sectional views illustrating a problem due to adiffraction exposure in a third mask process;

FIGS. 8A and 8B are SEM micrographs used to measure a photoresist filmafter a diffraction exposure;

FIGS. 9A through 9C are sectional views schematically illustrating aprocess flow of an LCD array substrate according to another embodimentof the present invention;

FIG. 10 is a partial plan view of a diffraction mask used in afabrication method of an LCD array substrate according to a secondembodiment of the present invention;

FIG. 11 is a magnified plan view of pixels of an LCD array substrateemploying a dual gate structure;

FIG. 12 is a partial plan view of a diffraction mask used in afabrication of the LCD array substrate of FIG. 11; and

FIGS. 13A and 13B are sectional views of a selected portion of FIG. 12.

DETAILED DESCRIPTION

The present invention will now be described with reference to theaccompanying drawings, in which exemplary embodiments of the inventionare shown.

FIGS. 4A through 4F are sectional views schematically illustrating aprocess flow of an LCD array substrate according to an embodiment of thepresent invention. FIGS. 4A through 4F can be compared with FIGS. 3Athrough 3G and show that the number of the masks used in the illustratedembodiment of the invention are reduced compared with that in therelated art process of FIGS. 3A through 3G.

Referring to FIG. 4A, a transparent insulating substrate 400 isprepared. Then, a thin polysilicon film is deposited then patterned by afirst mask process (not shown) to form an active layer 410. The activelayer 410 can be formed by depositing a thin amorphous silicon film onthe substrate and then crystallizing the deposited amorphous siliconfilm.

The amorphous silicon film can be deposited by a variety of methods,such as low pressure chemical vapor deposition (LPCVD) or plasmaenhanced chemical vapor deposition (PECVD).

The crystallization of the amorphous silicon film can be performed by asolid phase crystallization method or an eximer laser annealing (ELA)method. The ELA method uses a pulse type laser beam.

In addition to the aforementioned crystallization methods, a sequentiallateral solidification (SLS) method has been proposed and has beenwidely researched. The SLS method grows grains in a lateral direction togreatly enhance the crystallization characteristic.

The SLS method exhibits the tendency of the grains to grow in adirection perpendicular to a boundary between liquid phase silicon andsolid phase silicon. See, for example, Robert S. Sposili, M. A. Crowder,and James S. Im, Mat. Res. Soc. Symp. Proc. Vol. 452, 956-957, 1997.This method properly controls size and irradiation range of the laserbeam to laterally grow the grains up to a desired length, therebyincreasing the silicon grain size.

Alternatively, although not shown in the drawings, prior to forming theactive layer 410, a buffer layer such as a silicon dioxide (SiO₂) orsilicon nitride (Si_(x)N_(y)) may be formed on the substrate.

The buffer layer prevents impurities such as Na or the like frompenetrating into an upper layer during the process (particularly, duringthe crystallization).

After the crystallization of the amorphous silicon film, adehydrogenation process is performed to reduce the amount of hydrogenatoms in the amorphous silicon film.

Next, referring to FIG. 4B, a first insulating layer 420 and a firstmetal layer (not shown) are sequentially deposited on the substrate 400including the active layer 410. The first insulating layer 420 is a gateinsulating layer and is formed of silicon oxide or silicon nitride.Also, the metal layer is formed in a single layer of Al, Mo and Cu, or adual layer of Al and Mo. The deposited metal layer is then patterned bya second mask process (not shown) to form a gate electrode 430 over theactive layer 410.

Next, impurity ions are implanted into the active layer 410 using thegate electrode 430 as an implant mask to form a source region 410 a anda drain region 410 b at both edges of the active layer 410,respectively.

At this time, the electrical properties of the active layer 410 arevaried depending on the conductivity type of the implanted dopants. Forexample, when the implanted dopants are a Group III element such asboron (B), the active layer 410 serves as a component of a P-type TFT,whereas when the implanted dopants are a group V element such asphosphorous (P), the active layer 410 serves as a component of an N-typeTFT.

Alternatively, the active layer 410 may have lightly doped drain (LDD)regions at upper surfaces of the source and drain regions. The LDDregions are formed by implanting impurity ions into the active layer 410at a relatively low concentration-compared to the sources and drainregions.

Referring to FIG. 4C, after forming the source and drain regions 410 aand 410 b, a second insulating layer 440 and a transparent conductivelayer are sequentially deposited on a resultant structure of thesubstrate 400 including the gate electrode 430. These layers are thenpatterned by a third mask process (not shown) to form a first contacthole 460 exposing the source region 410 a, a second contact hole 462exposing the drain region 410 b, and a pixel electrode 450.

In the third mask process, since the first contact hole 460, the secondcontact hole 462, and the pixel electrode 450 are preferably formed inone mask process, a diffraction mask or a half-tone mask is used.

In accordance with an embodiment of the invention, the diffraction maskhas a slit structure having a plurality of slit regions corresponding tolight transmission regions. The amount of the light transmitting throughthe slit regions of the diffraction mask is smaller than thattransmitting through a full transmission region. Hence, when aphotoresist film is exposed using the diffraction mask having the slitregions and the full transmission regions, the thickness of thephotoresist film remaining in the slit regions is different than that ofthe photoresist film remaining in the full transmission regions.

In other words, when the photoresist film is a positive typephotoresist, the photoresist film which is exposed to the lightirradiated through the slit regions is formed thicker than that which isexposed to the light irradiated through the full transmission regions.When the photoresist film is a negative type, the photoresist film whichis exposed to the light irradiated through the full transmission regionsis formed thicker than that which is exposed to the light irradiatedthrough the slit regions.

In another embodiment of the invention, instead of the slit regions ofthe diffraction mask, half-tone regions are used to obtain the sameexposure effect.

In particular, in the present invention, the diffraction patterns, thatis, diffraction slits, are continuously arranged in a vertical directionor a horizontal direction to form a large-sized screen. As a result, thecontact holes and the pixel electrode can be concurrently formed by onemask process, which will be described in more detail with reference toFIGS. 5A through 5E.

Referring to FIG. 4D, after the first contact hole 460, the secondcontact hole 462, and the pixel electrode 450 are formed using the thirdmask process, a second metal layer (not shown) such as Mo, or Mo alloy(ex. MoTa, MoW) is deposited on a resultant structure of the substrate400.

The deposited second metal layer is patterned using a fourth maskprocess (not shown) to form a source electrode 470 and a drain electrode480. The source electrode 470 is electrically connected with the sourceregion 410 a through the first contact hole 460. Also, the drainelectrode 480 has one edge electrically connected with the drain region410 b through the second contact hole 462, and the other edgeelectrically connected with the pixel electrode 450. Also, the sourceelectrode 470 is also connected with the data line (not shown).

As described above, the LCD array substrate of the present invention isfabricated by four mask processes. Hence, compared with the fabricationmethod of the array substrate according to the related art, the presentembodiment can omit two mask processes. Accordingly, enhancement inproductivity and reduced production costs are obtained.

The present invention makes it possible to form a transmission type LCDthrough the processes of FIGS. 4A through 4D and can also combine therole of a reflection type LCD through added processes of FIGS. 4E and4F.

That is, as shown in FIG. 4E, a third insulating layer 490 is depositedon an entire surface of the substrate 400 including the source and drainelectrodes 470 and 480, and is then patterned to form a third contacthole 492. The third contact hole 492 partially exposes the drainelectrode 480 and exposes a transmission part T of the pixel electrode450.

Next, as shown in FIG. 4F, a second metal layer is deposited on thethird insulating layer 490 including the third contact hole 492 and isthen patterned by an added sixth mask process (not shown) to form areflection electrode 496, while exposing the transmission part T. Thereflection electrode 496 is electrically connected with the drainelectrode 480 through the third contact hole 492, and serves as areflection part R.

FIGS. 5A through 5E are sectional views illustrating an exemplary thirdmask process in a fabrication method of an LCD array substrate accordingto an embodiment of the present invention.

First, as shown in FIG. 5A, a second insulating layer 540 and atransparent conductive layer 552 are sequentially deposited on aresultant structure of a substrate 500 that includes a semiconductorlayer 500, a first insulating layer 520, and a gate electrode 530.Thereafter, a photoresist film 570 is coated on the transparentconductive layer 552. In the present embodiment, the second insulatinglayer 540 is a planarizing film made of organic insulating material.

Next, referring to FIG. 5B, the photoresist film 570 is exposed to alight by using a diffraction mask 580 according to an embodiment of thepresent invention. The diffraction mask 580 includes a firsttransmission region A1 for partially transmitting the incident light, asecond transmission region A2 for completely transmitting the incidentlight, and a blocking region A3 for completely blocking the incidentlight. Accordingly, the incident light is irradiated onto thephotoresist film 570 through the first transmission region A1 and thesecond transmission region A2 of the diffraction mask.

Next, referring to FIGS. 5B and 5C, the exposed photoresist film 570 isdeveloped, so that the photoresist film in the first transmission regionA1 and the blocking region A3 remains but the photoresist film in thesecond transmission region A2 is removed. Although the positivephotoresist film is exemplarily described, a negative photoresist filmcan be also used.

After developing the photoresist film 570, a first photoresist pattern572 is formed corresponding to the first transmission region A1, whichis thinner than a second photoresist pattern 574 corresponding to theblocking region A3.

The transparent conductive layer 552 and the second insulating layer 540are patterned by using the first and second photoresist patterns 572 and574 as a mask, thereby forming a first contact hole 560 and a secondcontact hole 562.

Next, referring to FIG. 5D, after the first and second contact holes 560and 562 are formed, the first photoresist pattern 572 is removed by anashing process. The second photoresist pattern 574 is also partiallyremoved such that its thickness is reduced.

Next, referring to FIG. 5E, the exposed conductive layer 552 is etchedby using the second photoresist pattern 574 as a mask, thereby forming apixel electrode 550. The second photoresist pattern 574 is then removedusing a stripper.

In the aforementioned third mask process, the first and second contactholes 560 and 562 and the pixel electrode 550 are formed by one maskprocess using the diffraction mask 580. In particular, the firsttransmission regions A1 each employing diffraction slits 582 arepositioned throughout an entire pixel region except for the regionswhere the first and second contact holes and the pixel electrode 550 areformed, as shown in FIG. 5B. For this purpose, the present inventionutilizes the diffraction mask capable of performing diffraction in alarge area, which will be described below in detail.

Although the embodiment set forth above describes a process in which thesecond insulating layer 540 is an organic insulating material, thesecond insulating layer can also be an inorganic material. As willsubsequently be described in connection with another embodiment of theinvention, when the second insulating layer is an inorganic material,step coverage problems can arise. In particular, because the inorganicmaterial is deposited as a thin layer, the inorganic film can becomevery thin in regions overlying previously formed metal layers.

FIG. 6 is a partial plan view of a diffraction mask used in afabrication method of an LCD array substrate according to an embodimentof the present invention. The diffraction mask is used in the third maskprocess described in FIG. 4C for a large-sized screen. Only a portion ofthe mask corresponding to a unit pixel region is shown. In particular,the diffraction mask of FIG. 6 is one designed for application to apositive photoresist film, but the present invention is not limitedthereto.

Referring to FIGS. 5B and 6, the diffraction mask 580 includes thesecond transmission region A2 for forming the contact hole, and theblocking region A3 for forming the pixel electrode. Also, thediffraction mask further includes the first transmission region A1having a plurality of slits 600 arranged continuously and having a largearea.

In FIG. 6, the slits 600 are arranged in a row direction. Alternatively,the slits 600 may be formed in a column direction or in the form ofdots.

Referring to FIGS. 5B through 5E, the second transmission region A2completely transmits the incident light such that contact holes 560 and562 partially exposing source and drain regions 510 a and 510 b areformed. The first transmission region A1 is formed in a diffractionpattern to partially transmit the incident light such that the pixelelectrode 550 is formed only at the blocking region A3.

As shown in FIG. 6, the diffraction pattern 600 of the firsttransmission region A1 includes bars 600 a for partially blocking lightand spaces 600 b for transmitting light. The bars 600 a or the spaces600 b may be designed to have a width ranging from about 1.0 μm to about2.0 μm and can be varied depending on the particular exposure apparatusand process recipe.

Although, the above embodiment shows and describes that the secondinsulating layer 540 is formed of an organic insulating material

Thus, when a metal layer exists below the diffraction-exposed region,the irradiated light is reflected by the metal, so that the photoresistfilm above the metal layer is made non uniform and thereby a processfailure may be caused.

FIGS. 7A through 7C are sectional views illustrating a drawback of thediffraction exposure in the third mask process.

With reference to these figures, which can be compared with theprocesses of FIGS. 5A through 5D, a drawback caused by a metal layerformed below the diffraction-exposed portion will be described for thecase where the gate electrode when the second insulating layer is madeof inorganic insulating material and not organic insulating material.

Referring to FIG. 7A, a second insulating layer 740 and a transparentconductive layer 752 are deposited on a substrate 700. The substrate 700includes an active layer 710, a first insulating layer 720, a gateelectrode 730, and a photoresist film 770 on the transparent conductivelayer 752. In this state, light is irradiated onto the photoresist film770 through a diffraction mask 780.

Then, since the second insulating layer 740 is made of inorganicinsulating material and is very thin compared with an organic insulatingmaterial, it exhibits a height difference due to the underlying metallayer or the like.

The diffraction mask 780 includes a first transmission region A1 forpartially transmitting incident light, a second transmission region A2for completely transmitting the incident light, and a blocking region A3for completely blocking the incident light. In the illustratedstructure, region B where the gate electrode 730 is formed has a heightdifference compared to the remaining portions of the device.

Next, the photoresist film that is exposed to the light through thediffraction mask 780 is developed to form a first photoresist pattern772 and a second photoresist pattern 774. That is, by developing thephotoresist film, the photoresist film is left at regions where thelight is irradiated through the first transmission region and theblocking region of the diffraction mask 780, but is removed at thesecond transmission region where the light is completely irradiated.

Next, referring to FIG. 7B, the exposed transparent conductive layer 752and the underlying second insulating layer 740 are sequentially etchedby using the first and second photoresist patterns 772 and 774 as amask, thereby forming a first contact hole 760 and a second contact hole762.

At this time, the first photoresist pattern 772 formed through the firsttransmission region A1 should be thinner than the second photoresistpattern 774 that was not exposed because of the presence of blockingregion A3.

Also, it is important that the first photoresist pattern 772 maintain auniform thickness so as to prevent failure in a subsequent etch process.

However, the light used for exposure of the photoresist film isreflected by the gate electrode 730. Accordingly, the thickness h1 ofthe photoresist film remaining on the gate electrode 730 is differentthan the thickness h2 of the photoresist film at a periphery of theregion A1.

Accordingly, as shown in FIG. 7C, when removing the first photoresistpattern 772 using an ashing process, the portion where the photoresistfilm is thin (portion C) overlying the gate electrode 730 and theconductive layer 752 formed beneath the photoresist pattern are alsoremoved. This is because the first photoresist pattern does not have auniform thickness thick enough to stop the etchment from attacking theunderlying metal.

The photoresist thinning is illustrated in the SEM micrographs of FIGS.8A and 8B.

The SEM micrographs are used to measure the photoresist film after adiffraction exposure. As shown in FIG. 8A, when a metal layer is notformed below the photoresist film, the photoresist film is 0.86 μm thickbut when a metal layer is formed below the photoresist film, thephotoresist film is 0.23 μm thick, which shows a considerabledifference.

In a second embodiment of the present invention to overcome the aboveproblem, in the diffraction exposure of the region where the metallayer, such as the gate electrode is formed, the width of the slit isreduced to decrease the amount of the light transmitted through theslit, thereby compensating for reflective thinning of the photoresistfilm.

It is noted that the second embodiment exemplifies that the secondinsulating layer of the LCD is made of a thin inorganic insulatingmaterial.

FIGS. 9A through 9C are sectional views schematically illustrating aprocess flow of an LCD array substrate according to another embodimentof the present invention. The fabrication method of an array substrateshown in FIGS. 9A through 9C is the same as that shown in FIG. 4 exceptthat the width of the slit is controllable in the third mask process.Hence, the fabrication method will be described centering on a processfor solving the problem mentioned in FIGS. 7A through 7C.

First, referring to FIG. 9A, a second insulating layer 940 and atransparent conductive layer 952 are deposited on a substrate 900including an active layer 910, a first insulating layer 920, a gateelectrode 930. Then, a photoresist film 970 is coated on the transparentconductive layer 952. In this state, light is irradiated onto thephotoresist film 970 through a diffraction mask 980.

Herein, since the second insulating layer 940 is made of inorganicinsulating material and is very thin compared with organic insulatingmaterial, it exhibits a height difference due to a underlying metallayer or the like.

The diffraction mask 980 includes a first transmission region A1 andthird transmission region A3 for partially transmitting incident light,a second transmission region A2 for completely transmitting the incidentlight, and a blocking region A3 for completely blocking the incidentlight.

As illustrated in FIG. 9A, a region D has a height difference where thegate electrode 930 is formed.

The present embodiment is characterized in that the width of the slitsin a predetermined portion A4 b of the third transmission region A4 isnarrower than those in a predetermined portion of the fourthtransmission region A4 a and the first transmission region A1 so as tocompensate for reflection from the gage electrode 930 which causes areduction in the thickness of the photoresist film at the portion thatoverlies the gate electrode 930.

In other words, the width of the slits in the normal first transmissionregion A1 and both ends A4 a of the fourth transmission region ispreferably about 1.2 μm, but the width of the slits in the portion A4 bof the fourth transmission region is preferably about 1.0 μm.

Thus, by reducing the width of the slits in the portion A4 b of thethird transmission region A4, the amount of the light used for exposureof the photoresist film is decreased, so that the photoresist film overthe gate electrode 930 experiences less reflective thinning.

Although the positive photoresist film is exemplarily described in thepresent embodiment, a negative photoresist film can be also used.

Next, referring to FIG. 9B, the photoresist film exposed to the lightthrough the diffraction mask 980 is developed to form a firstphotoresist pattern 972 and a second photoresist pattern 974. That is,by developing the photoresist film, the photoresist film is left atregions where the light is irradiated through the first transmissionregion A1, the third transmission region A4, and the blocking region A3of the diffraction mask 980, but is removed at the second transmissionregion A2 where the light is completely irradiated.

The exposed transparent conductive layer 952 and the underlying secondinsulating layer 940 are sequentially etched by using the first andsecond photoresist patterns 972 and 974 as a mask, thereby forming afirst contact hole 960 and a second contact hole 962.

As illustrated in FIG. 9B, the first photoresist pattern 972 formedthrough the first transmission region A1 is thinner than the secondphotoresist pattern 974 formed through the blocking region A3. Also, thediffraction exposure is performed by using the slit pattern, such thatthe third transmission region A4 has a difference in width so that thefirst photoresist pattern 972 can maintain a uniform thickness.

In other words, since the third transmission region A4 is provided withthe portion A4 b where the slit width is narrower and the portion A4 awhere the slit width is wider, the slit width of the diffraction mask inthe region where the gate electrode is formed is reduced to decrease theamount of the light transmitted through the corresponding region of thediffraction mask. By compensating for the reflection of the light by thegate electrode 930 and the height of the gate electrode 930, thethickness h3 of the photoresist film remaining over the gate electrode930 is nearly the same as the thickness h3 of the photoresist film inperipheral regions of the gate electrode 930.

Hence, as shown in FIG. 9C, when the first photoresist pattern 972 isremoved using an ashing process, the more uniform thickness of the firstphotoresist pattern 972 can overcome the process failure mentioned withreference to FIG. 8C. Also, after the ashing process, a portion 975 ofsecond photoresist pattern 974 remains on corresponding blocking regionA3.

In the third mask process described above, the contact holes and thepixel electrode are formed by one mask process. However, in the presentembodiment, the regions where the diffraction slits having the smallerslit width are applied are positioned to an entire region of the pixelregion except for the regions where the contact holes and the pixelelectrode are formed. For this purpose, the present invention utilizesthe diffraction mask capable of performing diffraction in a large area,which will be described below in detail.

FIG. 10 is a partial plan view of a diffraction mask for a large-sizedscreen used in a fabrication method of an LCD array substrate.Specifically, the illustrated mask is used in the third mask processaccording to another embodiment of the present invention, and only aportion of the mask corresponding to a unit pixel region is shown inFIG. 10.

In particular, the diffraction mask of FIG. 10 is designed for use witha positive photoresist film but the present invention is not limitedthereto.

Referring to FIGS. 9 and 10, the diffraction mask includes the secondtransmission region A2 for forming the contact holes, and the blockingregion A3 for forming the pixel electrode. Also, the diffraction maskfurther includes the first transmission region A1 and the fourthtransmission region A4 having a plurality of slits 1000 arrangedcontinuously over a large area.

The diffraction mask of FIG. 10 is characterized in that the slits 1000are not all arranged at a constant interval but are arranged at asmaller width at a region E where a metal layer, such as the gateelectrode 930 is formed (the fourth transmission region A4).

Also, in FIG. 10, the slits 1000 are arranged in a row direction.Alternatively, the slits 1200 may be formed in a column direction or inthe form of dots.

Referring to FIG. 10, the second transmission region A2 completelytransmits the incident light such that contact holes 960 and 962partially exposing source and drain regions are formed. The firsttransmission region A1 is formed in a diffraction pattern to partiallytransmit the incident light, such that the pixel electrode 950 is formedonly at the blocking region A3.

As shown in FIG. 10, the diffraction pattern having the firsttransmission region A1 and the fourth transmission region A4 includesbars 1000 a for partially blocking light and spaces 1000 b fortransmitting light. The spaces 1000 b preferably have a width rangingfrom about 1.0 μm to about 2.0 μm and can vary depending on the exposureapparatus and process recipe.

As described above, the interval between the spaces 1000 b, i.e., thewidth of the slit in the fourth transmission region A4, may be differentthan the interval between the spaces in other regions other than thefourth transmission region A3.

In other words, at the region A4 b where the metal layer is formed, thewidth of the slit is made narrow, and at the region A4 a where the metallayer is not formed, the width of the slit is comparatively wider.

As one example, the width of the slit in the region where the metallayer is formed is preferably designed to be about 1.0 μm, and the widthof the slit in the first portion A1 of the first transmission region A1is preferably designed to be about 1.2 μm.

Although the exemplarily embodiment of FIG. 9 shows and describes thatthe metal layer is the gate electrode, the present invention is notnecessarily limited to the metal layer. That is, it will be understoodto those skilled in the art that the present invention can be applied toa layer positioned below the photoresist film is not a metal, but causesa difference in the thickness of the photoresist film due to a heightdifference of the layer.

Also, the present invention can be applied to an LCD array substratehaving a dual gate structure. In the fabrication method of the LCD arraysubstrate having the dual gate structure, the diffraction mask isdesigned to have a region including slits having a narrow width so as tocorrespond to the region where a metal layer, such as the gateelectrode, is formed.

FIG. 11 is a magnified plan view of pixels of an LCD array substrateemploying a dual gate structure. Referring to FIG. 11, a gate line 1115and a data line 1103 are arranged to perpendicularly cross each other,and a thin film transistor (TFT) having a dual gate is formed at acrossing region of the gate line 1115 and the data line 1103.

The TFT includes an active layer 1111, gate electrodes 1115 a and 1115a′, and source and drain electrodes 1119 a and 1119 b.

A part of the active layer 1111 forms a lower electrode 1111′ of astorage capacitor, and the lower electrode 1111′ forms the storagecapacitor Cst together with an upper electrode 1112 formed on the lowerelectrode 1111′.

The gate electrode includes the first gate electrode 1115 a branchingfrom the gate line 1115, and the second gate electrode 1115 a′corresponding to a part of the gate line 1115 overlapping the activelayer 1111.

The source electrode 1119 a branches from the data line 1103 and iselectrically connected with a source region 1111 a through a firstcontact hole 1117 a. The drain electrode 1119 b has one end connectedwith the drain region 1111 b through a second contact hole 1117 b, andthe other end connected with a pixel electrode, i.e., with atransmission electrode formed on a transmission region T and areflection electrode formed on a reflection region R at the same time.

In the above array substrate, when a gate signal having a high voltagelevel is applied to the gate electrode, a channel serving as an electrontransfer path is formed in the active layer and thus data signals of thesource electrode are transferred to the drain electrode via the activelayer.

The storage capacitor charges a gate voltage while a gate signal isapplied to the gate electrode, and then discharges the voltage toprevent a voltage variation in the pixel electrode while a next gateline is driven and a data voltage is supplied to the pixel electrode.

Correspondingly, when a gate signal having a low voltage level isapplied to the gate electrode, the channel formed in the active layer isshut off and a signal transmission to the drain electrode is stopped.The use of the dual gate electrodes in the LCD can decrease leakagecurrent generated when a gate signal is shut off.

The dual gate electrodes can be applied to a transmission type LCD inwhich only a transmission electrode is formed on a pixel region, or areflection type LCD in which only a reflection electrode is formed on apixel region.

The present embodiment is characterized as described in FIGS. 4 through10 in that in forming an LCD array substrate having dual gateelectrodes, contact holes 117 a and 117 b and pixel electrode areconcurrently formed using one mask.

Also, the present embodiment is characterized in that in performing thediffraction exposure, the width of the diffraction slit at a regionwhere a metal layer such as the gate electrode is formed is madenarrower than that at a region where the metal layer is not formed,thereby uniformly controlling the thickness of the photoresist film.

FIG. 12 is a partial plan view of a diffraction mask used in afabrication of the LCD array substrate of FIG. 11, and shows thelarge-sized diffraction mask used in the third mask process. Inparticular, FIG. 12 shows a region of the diffraction mask correspondingto a unit pixel region. Although FIG. 12 shows and describes thediffraction mask designed to be applied to the positive photoresistfilm, its application is not limited only to the positive photoresistfilm.

Referring to FIGS. 11 and 12, the diffraction mask includes the secondtransmission region A2 for forming the contact hole, and the blockingregion A3 for forming the pixel electrode, and the like. Also, thediffraction mask further includes the first transmission region A1 andthe third transmission region A4 having a plurality of slits 1200arranged continuously and having a large area.

The diffraction mask of FIG. 12 is characterized in that the slits 1200are not all arranged at a constant interval, but the slits 1200 formedat the third transmission region A4 are arranged at a smaller widthcorresponding to a region where a metal layer, such as the gateelectrode or the gate line, is formed. Also, in FIG. 12, the slits 1200are arranged in a row direction. Alternatively, the slits 1200 may beformed in a column direction or in the form of dots.

The second transmission region A2 completely transmits the incidentlight such that contact holes partially exposing source and drainregions are formed. The first transmission region A1 and the thirdtransmission region A4 are formed in a diffraction pattern to partiallytransmit the incident light, such that the pixel electrode is formedonly at the blocking region A3.

The diffraction pattern having the first transmission region A1 and thethird transmission region A4 includes bars 1200 a for partially blockinglight and spaces 1200 b for transmitting light. The spaces 1200 bpreferably have a width ranging from about 1.0 μm to about 2.0 μm andcan vary depending on the exposure apparatus and recipe.

As described above, in the third transmission region A4, the intervalbetween the spaces 1200 b, i.e., the width of the slit, is not constant.In other words, at the region where the metal layer is formed, the widthof the slit is made narrow, and at the region where the metal layer isnot formed, the width of the slit is made wide comparatively.

As one example, the width of the slit in the region where the metallayer is formed is preferably about 1.0 μm, and the width of the slit inthe first portion A1 of the first transmission region A1 is preferablydesigned to be about 1.2 μm.

FIGS. 13A and 13B are sectional views of a selected portions of FIG. 12.FIG. 13A shows a sectional view taken along section line II-II′ of FIG.12 and FIG. 13B shows a sectional view taken along section line III-III′of FIG. 12.

FIGS. 13A and 13B illustrates an embodiment of the inention using apositive photoresist film. In describing FIGS. 13A and 13B, whereverpossible, the same reference numbers as those of FIGS. 9A through 9Cwill be used throughout the drawings to refer to the same or like parts,and their repeated detailed description will be omitted.

Referring to FIG. 13A, light completely transmits through a secondtransmission region A2 to expose the photoresist film so that theexposed photoresist film is completely removed by the developingprocess. Since the light is diffracted while passing through a firsttransmission region A1, the photoresist film corresponding to the firsttransmission region A1 is only partially removed by the developingprocess. Also, since a blocking region A3 of the diffraction mask blocksthe light, the photoresist film corresponding to the blocking region A3is not exposed and consequently is not removed by the developingprocess.

In the present embodiment, slits formed at the first transmission regionA1 are not all formed at a constant interval as shown in FIG. 13B. Inother words, the diffraction mask shown in FIG. 13B is characterized inthat the slits are arranged at a smaller width at a region F where ametal layer such as the gate electrode or the gate line is formed,thereby uniformly controlling the thickness of the photoresist film.

If all the slits of the first transmission region are formed at an equalinterval, the light used for exposure of the photoresist film isreflected by a metal layer, such as the gate electrode, and a thicknessh1 of the photoresist film remaining on the gate electrode is differentthan a thickness h2 of the photoresist film at a periphery, as describedabove with reference to FIGS. 7A through 7C.

To solve the above problems, the width of the slits at the region A4where the metal layer is formed is made narrower as shown in FIG. 13B.As described above, according to an array substrate of an LCD andfabrication method thereof, a contact hole exposing a drain region of aTFT and a pixel electrode are formed by one mask process, therebysimplifying the fabrication process and enhancing the productivity.Also, a large-sized diffraction mask having slits of which widths arecontrolled depending on whether there exists a metal layer below adiffraction-exposed portion is provided, thereby controlling thethickness of the photoresist film during the diffraction exposure.

It will be apparent to those skilled in the art that variousmodifications and variations can be made in the present invention. Thus,it is intended that the present invention covers the modifications andvariations of this invention provided they come within the scope of theappended claims and their equivalents.

1. An array substrate of an LCD comprising: a substrate; an active layeron the substrate, a first insulating layer overlying the active layer,and a gate electrode overlying the first insulating layer; a sourceregion and a drain region reside in predetermined regions of the activelayer and each is doped with impurity ions; a second insulating layeroverlying an entire surface of the substrate including the gateelectrode; a pixel electrode on the second insulating layer; first andsecond contact holes in the first and second insulating layer andexposing portions of the source region and the drain regions,respectively; a source electrode of which a portion contacts the sourceregion through the first contact hole; and a drain electrode of which afirst portion contacts the drain region and a second portion contactsthe pixel electrode.
 2. The array substrate of claim 1, wherein theactive layer comprises polysilicon.
 3. The array substrate of claim 1,further comprising a buffer layer below the active layer.
 4. The arraysubstrate of claim 1, wherein the pixel electrode and the first andsecond contact holes are formed by using a mask provided with adiffraction pattern.
 5. The array substrate of claim 4, wherein thediffraction pattern transmits only a portion of incident light ontoregions other than regions where the pixel electrode and the first andsecond contact holes reside.
 6. The array substrate of claim 4, whereinthe diffraction pattern has a slit width ranging from about 1.0 μm toabout 2.0 μm.
 7. The array substrate of claim 6, wherein the slit widthof a corresponding diffraction pattern varies in regions where a metallayer exists on the substrate.
 8. The array substrate of claim 7,wherein the second insulating layer comprises inorganic material.
 9. Thearray substrate of claim 7, wherein the corresponding diffractionpattern has a slit width of about 1.0 μm and the diffraction patternover a region not having the metal layer has the slit width of about 1.2μm.
 10. The array substrate of claim 1, further comprising: a thirdinsulating layer overlying an entire surface of the substrate includingthe source electrode and the drain electrode; a third contact hole in apredetermined region of the third insulating layer that exposes aportion of the drain electrode; and a reflection electrode on the thirdinsulating layer and electrically connected to the drain electrodethrough the third contact hole.
 11. The array substrate of claim 1,wherein the gate electrode comprises a first gate electrode branchingfrom a gate line, and a second gate electrode, which comprises a portionof the gate line overlapping the active layer.
 12. A method offabricating an array substrate of an LCD, the method comprising:sequentially forming an active layer, a first insulating layer, and agate electrode on a substrate; forming a source region and a drainregion on predetermined regions of the active layer by implantingimpurity ions into the predetermined regions of the active layer;forming a second insulating layer on an entire surface of the substrateincluding the gate electrode; forming a pixel electrode on the secondinsulating layer, and forming first and second contact holes by removingportions of the first and second insulating layer overlying the sourceregion and the drain region; forming a source electrode of which aportion contacts the source region through the first contact hole; andforming a drain electrode of which a first portion contacts the drainregion and a second portion contacts the pixel electrode.
 13. The methodof claim 12, wherein the forming the pixel electrode and the first andsecond contact holes comprises: forming a transparent conductive film onthe second insulating layer; coating a photoresist film on thetransparent conductive film; irradiating a light onto the coatedphotoresist film using a mask having a first transmission regionpartially transmitting the light, a second transmission regioncompletely transmitting the light, and a blocking region thatsubstantially blocks the light; developing the photoresist film exposedto the light to form a first photoresist pattern corresponding to thefirst transmission region and a second photoresist pattern correspondingto the shielding region; partially removing the first insulating layer,the second insulating layer, and the transparent conductive film usingthe first and second photoresist patterns as a mask to form the firstand second contact holes; removing the first photoresist pattern; andpatterning the transparent conductive film using the second photoresistpattern as a mask to form the pixel electrode.
 14. The method of claim13, wherein the first transmission region has a diffraction pattern forpartially transmitting the light that is incident into regions otherthan the regions where the first and second contact holes are beingformed.
 15. The method of claim 13, wherein the first transmissionregion has a halftone pattern for partially transmitting the light thatis incident into a region other than regions where the first and secondcontact holes are being formed.
 16. The method of claim 14, wherein thediffraction pattern comprises a slit-shaped bar for partially shieldingthe light and a space for transmitting the light.
 17. The method ofclaim 14, wherein the diffraction pattern has a slit width ranging fromabout 1.0 μm to about 2.0 μm.
 18. The method of claim 13, wherein theslit widths of the diffraction pattern have a difference such that thephotoresist pattern has a substantially uniform thickness.
 19. Themethod of claim 18, wherein the slit widths of the diffraction patterndiffer where a metal layer exists on a region of the substratecorresponding to the diffraction pattern.
 20. The method of claim 18,wherein the second insulating layer comprises an inorganic material. 21.The method of claim 19, wherein the diffraction pattern over the metallayer has the slit width of about 1.0 μm and the diffraction patternover a region not having the metal layer has the slit width of about 1.2μm.
 22. The method of claim 21, wherein the metal layer comprises a gateelectrode.
 23. The method of claim 12, further comprising: forming athird insulating layer overlying an entire surface of the substrateincluding the source electrode and the drain electrode; removing apredetermined portion of the third insulating layer to form a thirdcontact hole exposing a predetermined region of the third insulatinglayer, and exposing the pixel electrode; and forming a reflectionelectrode electrically connected with the drain electrode through thethird contact hole on the third insulating layer.
 24. The method ofclaim 12, wherein the gate electrode comprises a first gate electrodebranching from a gate line, and a second gate electrode, which comprisesa portion of the gate line overlapping the active layer.
 25. A method offabricating an array substrate of an LCD, the method comprising: formingan active layer on a substrate using a first mask process; depositing afirst insulating layer and a first metal layer on the substrateincluding the active layer and patterning the first metal layer using asecond mask process to form a gate electrode; forming a source regionand a drain region on predetermined regions of the active layer byimplanting impurity ions into the predetermined regions of the activelayer; depositing a second insulating layer and a transparent conductivefilm on an entire surface of the substrate including the gate electrode,and removing portions of the first and second insulating layers and thetransparent conductive film using a third mask process to form first andsecond contact holes partially exposing the source and drain electrodes,and a pixel electrode; and depositing a second metal layer on thesubstrate and patterning the second metal layer using a fourth maskprocess to form a source electrode and a drain electrode, such that thesource electrode is connected to the source region through the firstcontact hole and the drain electrode is connected to the drain electrodethrough the second contact hole.
 26. The method of claim 25, wherein thepixel electrode and the first and second contact holes are formed usinga mask comprising a diffraction pattern.
 27. The method of claim 26,wherein the diffraction pattern partially transmits incident lightthrough regions other than the regions where the pixel electrode and thefirst and second contact holes are being formed.
 28. The method of claim27, wherein slit widths of the diffraction pattern differ when a metallayer exists on a region of the substrate corresponding to thediffraction pattern.
 29. The method of claim 28, wherein the secondinsulating layer comprises an inorganic material.
 30. The method ofclaim 25, wherein the gate electrode comprises a first gate electrodebranching from a gate line, and a second gate electrode, which comprisesa portion of the gate line overlapping the active layer.
 31. A method offabricating an array substrate of an LCD, the method comprising:providing a substrate having an insulating layer overlying a patternedmetal layer; forming a resist layer overlying the insulating layer; andaligning a mask to the substrate, wherein the mask has a variation indiffraction density, and wherein the mask is aligned such that an areaof high diffraction density is in spaced relationship with the patternedmetal layer.
 33. The method of claim 31, wherein the insulating layercomprises an inorganic material.
 34. The method of claim 31, whereinaligning a mask comprises aligning a mask having a diffraction patternthat includes slit widths ranging from about 1.0 μm to about 2.0 μm. 35.The method of claim 34, wherein the diffraction pattern in spacedrelationship with the patterned metal layer has a slit width of about1.0 μm, and the diffraction pattern over a region not having thepatterned metal layer has slit widths of at least about 1.2 μm.